We are developing a RISC-V rv32im / ilp32 core. Eventually it will support the atomic and compressed instructions. However at this point it does not. For reasons beyond this discussion, that means that the autoconf build isn't going to work for me right now. This leaves me with the second build option WOLF_USER_SETTINGS. I am able to build the library using this method.
I looked at the .../IDE/RISCV settings. This directory should be called .../IDE/SIFIVE-RISCV. The defines in the HIFIVE directory are specific to the the E310 (rv32imac). Unfortunately this won't work for my project. Ideally I would be able to select the RISCV core configuration and wouldn't be tied to a specific vendor / chip.
I looked at the examples/configs. The closest thing is the stm32. However there is quite a bit of STM32Fxxx / Cube specifics. Ideally there would be a 32-bit / little endian / hardware multiplier / XMALLOC example that I could build on.
Is there a generic 32-bit / little endian / hardware multiplier / XMALLOC example that doesn't have any processor specifics in it?
Is there a "configuration guide" that goes through the settings and describes what they do and why I might need them?