The Agilex Family and Agilex 5
The Altera Agilex portfolio represents a family of modern SoC FPGAs designed to address the scaling and power efficiency requirements of edge, data center, and communication infrastructures. Built on advanced process technologies, the family unifies programmable logic with hardened processor subsystems, high-bandwidth memory interfaces, and specialized digital signal processing (DSP) blocks optimized for vector math and AI workloads.
Within this portfolio, the Agilex 5 series specifically targets mid-range applications where power constraints and high performance must coexist at the edge. A defining feature of the Agilex 5 is its asymmetric hard processor subsystem (HPS). Unlike traditional homogeneous multi-core architectures, Agilex 5 pairs power-efficient cores with high-performance cores in a single compute cluster.
Benchmarks
Hardware and Environment:
- Hardware: Terasic DE-25 Nano (Agilex 5 A5EB013BB23BE4SR1).
- Host OS: Linux 6.12.11-altera fork.
- CPUs: Cortex-A55 core (2 @1.25 GHz) and Cortex-A76 core (2 @1.40 GHz).
- Benchmark Software: wolfSSL 5.9.1 benchmark.c compiled with GCC + O2.
- Block Bytes: 1048576
- Time per Algo: ~1.0 sec each
Charts:
If you have questions about any of the above, please contact us at facts@wolfssl.com or call us at +1 425 245 8247.
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